Exploring Performance and Cost Optimization with ASIC-Based CXL Memory


As memory-intensive applications continue to drive the need for advanced architectural solutions, Compute Express Link (CXL) has risen as a promising interconnect technology that enables seamless high-speed, low-latency communication between host processors and various peripheral devices. In this study, we explore the application performance of ASIC CXL memory in various data-center scenarios. We then further explore multiple potential impacts (e.g., throughput, latency, and cost reduction) of employing CXL memory via carefully designed policies and strategies. Our empirical results show the high potential of CXL memory, reveal multiple intriguing observations of CXL memory and contribute to the wide adoption of CXL memory in real-world deployment environments. Based on our benchmarks, we also develop an Abstract Cost Model that can estimate the cost benefit from using CXL memory.

Proceedings of the Nineteenth European Conference on Computer Systems (EuroSys 24 Best Paper Runner-Up)
Yupeng Tang
Yupeng Tang
Final-year PhD student @ Yale University

My research interests include distributed systems, memory disaggregation and hardware accelerators.